1. Field of the Invention
This invention relates generally to the testing of memory devices, and more particularly to the testing of memory devices using a compression circuit.
2. Description of the Related Art
Memory devices, such as a synchronous dynamic random access memory (SDRAM), are being developed with ever-increasing densities. During the manufacturing process, the memory device is tested to verify proper operation. If improperly functioning cells are identified, the memory device may be repaired or discarded, depending on the number, type, and arrangement of faulty memory cells. Also, if a sample of memory devices is tested and the individual memory devices are found to have faults in common locations, certain stages in the manufacturing process may be examined and/or altered to correct possible systemic defects.
As the density of memory devices increases, the time required to test the devices also increases. Compression circuits have been developed to simultaneously test blocks of memory cells and provide information regarding the success or failure of the test. A test using a compression circuit indicates that one of the cells in the block of cells is faulty. Further testing is required to identify the specific cell. Typically, the further test involves a time consuming cell-by-cell test to identify the faulty cell.
FIG. 1 illustrates a logic diagram of a prior art compression circuit 10. The compression circuit 10 of FIG. 1 receives sixteen input lines, D1–D16 (e.g., I/O lines) and provides an output based on the success of the test. The compression circuit 10 includes a first portion 14 adapted to provide an indication that all logic ones are present on the input lines D1–D16, and a second portion 16 adapted to provide an indication that all logic zeros are present on the input lines D1–D16. If any of the input lines D1–D16 on the first portion 14 receive a logic “0”, the first portion 14 of the compression circuit 10 will indicate a fail condition. Likewise, if any of the input lines on the second portion 16 receives a logic “1”, the second portion 14 of the compression circuit 10 will indicate a fail condition.
The first portion 14 of the compression circuit 10 includes an arrangement of NAND gates 18, NOR gates 20, and an inverter 22 that collectively perform a logical 16-bit wide NAND function. Conversely, the second portion 16 of the compression circuit 10 includes NOR gates 24, NAND gates 26, and an inverter 28 that collectively perform a logical 16-bit wide NOR function. The compression ratio of the compression circuit 10 may be altered by increasing or decreasing the number of cascaded rows of NAND gates 18, 24 and NOR gates 20, 26.
The compression circuit 10 also includes an output circuit 30 adapted to tailor the output format into one of two output modes, tristate and JEDEC. The JEDEC mode of operation corresponds to a mode of error detection defined by Joint Electron Device Engineering Council (JEDEC) standards. The output circuit 30 includes multiplexers 32, 33 that are enabled during the tristate mode of operation, and multiplexers 34, 35 that are enabled during the JEDEC mode of operation. Mutually exclusive logic signals, TRI and JED on lines 36, 37, respectively, determine the particular multiplexers 32, 33, 34, 35 that are enabled.
To operate in the tristate output mode, the TRI signal is held at a logically high state to enable the multiplexers 32, 33. The JED signal is held at a logically low state to disable the multiplexers 34, 35. The multiplexer 32 receives the output of the first portion 14 of the compression circuit 10, where the first portion 14 outputs a logic “0” to indicate a pass condition and a logic “1” to indicate a fail condition. The output of the multiplexer 32 is coupled to the gate input of a p-type transistor 38. The transistor 38 is connected between a voltage source 39 (e.g., about 2.2V) and an output terminal 40. When the first portion 14 of the compression circuit 10 indicates a pass condition (i.e., logic “0”), the transistor 38 is enabled and the voltage at the output terminal 40 is pulled to a logically high state by the voltage source 39. During a fail condition (i.e., logic “1”) the transistor 38 is disabled, disconnecting the power source 39 from the output terminal 40.
The multiplexer 33 receives the output of the second portion 16 of the compression circuit 10, where the second portion 16 outputs a logic “1” to indicate a pass condition and a logic “0” to indicate a fail condition. The output of the multiplexer 33 is coupled to the gate input of an n-type transistor 42. The transistor 42 is connected between the output terminal 40 and ground. When the second portion 16 of the compression circuit 10 indicates a pass condition (i.e., logic “1”), the transistor 42 is enabled and the voltage at the output terminal 40 is pulled to a logically low state. During a fail condition (i.e., logic “0”) the transistor 42 is disabled, disconnecting the output terminal 40 from ground.
The portion 14, 16 of the compression circuit 10 that indicates a passing condition will control the voltage on the output terminal 40. The voltage on the output terminal 40 is read to determine the success or failure of the test. The value on the output terminal 40 of the compression circuit 10 matches the actual value that was written to the cells during the test. For example, if all logic “1” values were successfully read from the memory device, the first portion 14 would pass and the second portion 16 would fail. The compression circuit 10 would output a logic “1” to indicate the successful test. Conversely, if all logic “0” values were successfully read from the memory device, the second portion 16 would pass and the first portion 14 would fail. The compression circuit 10 would output a logic “0” to indicate the successful test. If both portions 14, 16 indicate a fail condition, the output terminal 40 is tristated and has a voltage of about 1.1V.
To operate in the JEDEC output mode, the JED signal is held at a logically high state to enable the multiplexers 34, 35, and the TRI signal is held at a logically low state to disable the multiplexers 32, 33. The outputs of the first and second portions 14, 16 of the compression circuit 10 are received by an XOR gate 44. In the circuit of FIG. 1, the XOR gate 44 is a two input gate, however, the actual transistors (not shown) that define the XOR gate 44 require the both the input signal and its compliment to operate. Accordingly, the output of the inverter 22, its compliment (i.e., the input to the inverter 22), the input of the inverter 28, and its compliment (i.e., the output of the inverter 28) are provided to the XOR gate 44. Unlike the example described above for the tristate mode, the input of the inverter 28 indicates pass or fail as opposed to the output of the inverter 28. Accordingly, a pass condition is denoted by a logic “0” at the input of the inverter 28.
The output of the XOR gate 44 is inverted by an inverter 46. The output of the inverter 46 is provided to the multiplexers 34, 35. If only one of the first and second portions 14, 16 of the compression circuit 10 indicates a pass condition (i.e., one portion 14, 16 has a logic “0” and the other has a logic “1”), the XOR gate 44 outputs a logic “1”, which is inverted by the inverter 46. The resulting logic “0” is provided to the multiplexers 34, 35, thus enabling the transistor 38 and pulling the voltage at the output terminal 40 to a logically high state. Conversely, if both the first and second portion 14, 16 pass or both fail, the XOR gate 44 outputs a logic “0”, which is inverted by the inverter 46. The resulting logic “1” is provided to the multiplexers 34, 35, thus enabling the transistor 42 and pulling the voltage at the output terminal 40 to ground.
FIG. 2 is a timing diagram of the response of the compression circuit 10 to various passed and failed tests. In the tristate mode of operation, the TRI signal 50 is held at a logically high state. The JED signal (not shown) is held at a logically low state. A failure signal 52 is used to simulate a test failure. During alternating tests, the compression circuit output signal 54 alternates between a logic “1” level and a logic “0” level to indicate the successful logic “1” tests and logic “0” tests. During a simulated failure 56, both the first portion 14 and the second portion 16 indicate a failed condition and the compression circuit output signal 54 is tristated.
In the JED mode (JEDEC), the ACT signal 50 is held at a logically low state. The JED signal (not shown) is held at a logically high state. During alternating tests the compression circuit output signal 54 maintains a logic “1” level to indicate the successful logic “1” tests and logic “0” tests. During a simulated failure 58, both the first portion 14 and the second portion 16 indicate a failed condition on successive tests and the compression circuit output signal 54 transitions to a logic “0” state to indicate the failure.
Compression circuits are typically included on the die of the memory device along with the memory device core. In embedded devices with multiple memory cores, each core typically has its own compression circuitry. The compression circuit typically receives inputs from a plurality of local or intermediate input/output (I/O) lines and provides an output indicating that either all lines passed or one of the lines failed. One or more compression circuits may be used, depending on the degree of desired compression. For example, if it was desired to simultaneously test 64 lines, and each compression circuit was adapted to receive eight input lines, eight compression circuits would be required.
The outputs of the compression circuit are typically tied to the external data in/data out (DQ) lines of the memory device. Changes in the memory device density and/or architecture of the memory device often require that the routing and logic gate arrangement of the compression circuit be redesigned.
During the testing process, the compression circuit adds a finite amount of delay to the stage of the memory device including the compression circuit. In a three cycle latency memory device, the compression circuit is typically included in the third stage, prior to the DQ outputs. Consider the case where, without the compression circuit enabled, the time required to complete the third stage is equal to or less than the time to complete the other two stages. The overall speed of the memory device is determined by the longest stage (i.e., the clock used to drive the memory device cannot have a period shorter than the length of the slowest stage). Now, add the additional delay contributed by the compression circuit (i.e., logic gate propagation times) to the third stage. With the additional delay, the third stage may become the speed limiting stage, and as a result, the speed of the memory device may need to be downgraded because the memory device cannot be tested at full speed. Reducing the clock frequency of the input clock used to test the memory device also lengthens the amount of time required to test the memory device.
As is common in memory device design, the memory device may have lines with differing data topologies. For example, if a logic “1” is written into a cell of a first topology type, a logic “1” is stored in the cell. If the same logic “1” is written into a cell of a second topology, a logic “0” may actually be stored in the cell. During the testing of the memory device, lines of one topology type may not be compressed with lines of a second topology type.
One of the lines coupling the memory device to the compression circuit may be shorted to another of the lines. If all the lines of the same topology type were to run in parallel from the memory device to the compression circuit, it is possible that the compression circuit might illegally pass the test (i.e., fail to detect the fault). Another possible error might arise due to capacitive coupling between adjacent lines. For example, if sixteen adjacent lines are coupled to one compression circuit, capacitive coupling could occur between the lines. A failed line may be coupled by the other fifteen lines, which are going to a logically high state, and forced to a logically high state. Coupling of this nature could disguise faults in the memory device.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.